Multi-layer graphene FET compact circuit-level model with temperature effects

This paper presents a circuit-level model of a dual-gate bilayer and four layer graphene field effect transistor (GFET). The model provides an accurate estimation of the conductance at the charge neutrality point (CNP). At the CNP the device has its maximum resistance, at which the model is validated against experimental data of the device off-current for a range of electric fields perpendicular to the channel. The model shows a good agreement for validations carried out at constant and varying temperatures. Using the general Schottky equation, the model estimates the amount of bandgap opening created by the application of an electric field. Also the model shows good agreement when validated against experiment for the channel output conductance against varying gate voltage for both a bilayer and four layer graphene channel

A circuit model for defective bilayer graphene transistors

This paper investigates the behaviour of a defective single-gate bilayer graphene transistor. Point defects were introduced into pristine graphene crystal structure using a tightly focused helium ion beam. The transfer characteristics of the exposed transistors were measured ex-situ for different defect concentrations. The channel peak resistance increased with increasing defect concentration whilst the on–off ratio showed a decreasing trend for both electrons and holes. To understand the electrical behaviour of the transistors, a circuit model for bilayer graphene is developed which shows a very good agreement when validated against experimental data. The model allowed parameter extraction of bilayer transistor and can be implemented in circuit level simulators.<br/

An Improved Throughput for Non-Binary Low-Density-Parity-Check Decoder

Low-Density-Parity-Check (LDPC) based error control decoders find wide range of application in both storage and communication systems, because of the merits they possess which include high appropriateness towards parallelization and excellent performance in error correction. Field-Programmable Gate Array (FPGA) has provided a robust platform in terms of parallelism, resource allocation and excellent performing speed for implementing non-binary LDPC decoder architectures. This paper proposes, a high throughput LDPC decoder through the implementation of fully parallel architecture and a reduction in the maximum iteration limit, needed for complete error correction. A Galois field of eight was utilized alongside a non-uniform quantization scheme, resulting in fewer bits per Log Likelihood Ratio (LLR) for the implementation. Verilog Hardware Description Language (HDL) was used in the description of the non-binary error control decoder. The propose decoder attained a throughput of 10Gbps at 400-MHz clock frequency when synthesized on a ZYNQ 7000 Series FPGA

Development of Hybrid Automatic Segmentation Technique of a Single Leaf from Overlapping Leaves Image

The segmentation of a single leaf from an image with overlapping leaves is an important step towards the realization of effective precision agricultural systems. A popular approach used for this segmentation task is the hybridization of the Chan-Vese model and the Sobel operator CV-SO. This hybridized approach is popular because of its simplicity and effectiveness in segmenting a single leaf of interest from a complex background of overlapping leaves. However, the manual threshold and parameter tuning procedure of the CV-SO algorithm often degrades its detection performance. In this paper, we address this problem by introducing a dynamic iterative model to determine the optimal parameters for the CV-SO algorithm, which we dubbed the Dynamic CV-SO (DCV-SO) algorithm. This is a new hybrid automatic segmentation technique that attempts to improve the detection performance of the original hybrid CV-SO algorithm by reducing its mean error rate. The results obtained via simulation indicate that the proposed method yielded a 1.23% reduction in the mean error rate against the original CV-SO method

Graphene FET circuit-level device modelling

This thesis presents models for a graphene based field effect transistor (GFET). The graphene material has been widely studied since its synthesis in 2004 and the material holds promise for the next generation electronic applications. Therefore, there is a need to model its device characteristics.In this respect the contributions presented here are, firstly, a SPICE-compatible model for both dual gate and single gate graphene transistors. The derivation of the carrier transport of both hole and electron conduction results in a set of analytical equations. These derivations cover the three identified regions of operation as well as the boundary voltage conditions that define the regions. The Jacobian entries are shown to be continuous across the region boundaries.Secondly, circuit levels model of a single-layer GFET and multi layer GFET suitable for a direct implementation in SPICE. In this contribution, a more accurate threshold voltage compared to other models is derived. This contribution also shows how models can be extended to as many layers the graphene channelled transistor has.Finally, the introduction of a thermionic resistance, which is modelled in parallel with the resistance due to gate induced charges, provides a model for the temperature dependent channel resistance. The contribution goes further to derive equations between the off current and the vertical electric fields. Thus, giving a good estimation of the tunable bandgap opening in graphene.The models in this contributions are validated against experimentally measured transistor characteristics which have been carried out by other research groups and the models show a good agreement in all cases validated. The thesis equally presents the use of a floating gate to optimize the transistors characteristics. To illustrate these contributions, algorithms of the models have been implemented on the following CAD tools, HSPICE, VHDL-AMS and Berkeley SPICE. During the course of this work one journal and five conference papers have been published

A floating gate graphene FET complementary inverter with symmetrical transfer characteristics

This paper presents the concept of a bilayer graphene transistor using a floating gate to achieve the necessary threshold potential required for symmetrical transfer characteristics in complementary inverters. Using the charge injected into the floating-gate, the threshold voltage of the channel can be controlled. The control of the channel's electrostatic doping using a floating-gate is exploited to simulate an inverter which shows a symmetrical transfer characteristic centred at an input voltage of Vdd/

Inhibitory activity of seed extract from Picralima nitida, (Staph) on &beta;-D-glucosidase

The rate of hydrolysis of p- nitrophenyl &#946;-D- glucopyranoside (PNPG) by &beta;-D glucosidase (&beta;-D-glucoside glucohydrolase, E.C. 2.1.21) from African giant snail (Achatina achatina) has been studied in the presence of seed extracts from Picralima nitida (Staph) Th&H.D. A at a substrate concentration range of 0.04-0.2mM there was no product (P- nitrophenol) inhibition of the enzyme. The Km and Vmax values for PNPG were calculated from Line Weaver-Burk plots and the values obtained were 0.214mM and 125-nmol/mg protein/min respectively. &beta;-glucosidase from Achatina achatina degraded PNPG faster than, that from such as Aspergillus niger Humicola grisea and Geotricum. spp The alkaloid extracts from the mature seeds of Picralima nitida inhibited the enzyme in a competitive manner with inhibitor equilibrium constant (ki) values of 0.263, 0.157.0.125 and 0.10mg/1 for alkaloid (inhibitor) concentrations of 4,6,8 and 10mg./l respectively. The biochemical implication of this study is that since the seeds extract showed inhibition of enzyme activity, the exploitation of this potential could be of immense value in the current search for new therapeutically effective drugs with inhibitory effects against &beta;-glucosidae which is implicated in HIV infectivity of cells. Key Words: &beta;-D-glucosidase, P. nitida, inhibition, HIV infectivity Biokemistri Vol.16(2) 2004: 72-7